1. Field of the Invention
This invention relates to integrated circuit memories and, more specifically, to a random access memory (RAM) with spare bit lines for use in place of defective bit lines.
2. Art Background
Random access memories (RAM) are common devices used in computers and many other modern digital systems. When a monolithic RAM is fabricated, errors in the fabrication process may render elements of the RAM defective. To avoid accessing the defective elements of the RAM, the defective elements are determined by testing and are then bypassed. The RAM is tested by writing and reading test data to all of the memory cells in the RAM. The memory cells in a RAM are accessed by row and column, where a column corresponds to the bit lines across a particular cell and a row corresponds to the word line of a cell. RAM memories typically divide the columns into separate arrays, and each array has a corresponding input/output driver. Frequently, it is sufficient to test only the columns in a RAM to determine whether a particular memory cell may be properly accessed. The defective columns are bypassed to insure integrity of the RAM.
Typically, in the prior art, defective columns are bypassed by a corresponding spare column fabricated on the RAM. When a RAM chip is fabricated, a spare column is fabricated for each array of columns on the chip. If one of the columns in a particular array is defective, the defective column is bypassed and the spare column is mapped to the corresponding input/output driver. Thus, there is typically one spare column for each input/output driver. The technique of bypassing defective columns with spare columns is known as column redundancy.
Fabricating one spare column for each input/output driver significantly increases the size of the fabricated chip where there are a relatively large number of column arrays. Modern fabrication techniques are such that most of the column arrays contain no defective columns, and thus the associated spare column for such arrays occupies space on the wafer and serves no purpose. Since miniaturization is an important goal in chip fabrication, a more efficient column redundancy scheme is desirable.
The present invention provides a more efficient column redundancy scheme by enabling a particular column to be mapped to more than one array of columns, thus decreasing the required number of spare columns and reducing the size of the chip.